PCA9502_3

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 13 October 2006

11 of 25

NXP Semiconductors

PCA9502

9.3 Addressing

Before any data is transmitted or received, the master must send the address of the

receiver via the SDA line. The first byte after the START condition carries the address of

the slave device and the read/write bit. Table 11 shows how the PCA9502’s address can

then the PCA9502’s address is set to 0x90, and the master communicates with it through

this address.

[1]

X = logic 0 for write cycle; X = logic 1 for read cycle.

9.4 Use of sub-addresses

When a master communicates with the PCA9502 it must send a sub-address in the byte

following the slave address byte. This sub-address is the internal address of the word the

master wants to access for a single byte transfer, or the beginning of a sequence of

locations for a multi-byte transfer. A sub-address is an 8-bit byte. Unlike the device

address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus

it must be followed by an acknowledge.

A register write cycle is shown in Figure 10. The START is followed by a slave address

byte with the direction bit set to ‘write’, a sub-address byte, a number of data bytes, and a

STOP signal. The sub-address indicates which register the master wants to access. and

the data bytes which follow will be written one after the other to the sub-address location.

Table 11.

PCA9502 address map

A1

A0

0x90 (1001 000X)

0x92 (1001 001X)

SCL

0x94 (1001 010X)

SDA

0x96 (1001 011X)

0x98 (1001 100X)

0x9A (1001 101X)

SCL

0x9C (1001 110X)

SDA

0x9E (1001 111X)

SCL

0xA0 (1010 000X)

SCL

0xA2 (1010 001X)

SCL

SCL

0xA4 (1010 010X)

SCL

SDA

0xA6 (1010 011X)

SDA

0xA8 (1010 100X)

SDA

0xAA (1010 101X)

SDA

SCL

0xAC (1010 110X)

SDA

SDA

0xAE (1010 111X)