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PM6541 데이터시트(PDF) 21 Page - PMC-Sierra, Inc |
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PM6541 데이터시트(HTML) 21 Page - PMC-Sierra, Inc |
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21 / 49 page ![]() PMC-Sierra, Inc. PM6541 E1XC-EVBD TELECOM STANDARD PRODUCT PMC-930917 ISSUE 1 E1XC EVALUATION DAUGHTERBOARD 18 C048H C148H PMON TSB Control/Status C049H C149H PMON TSB FER Count C04AH C14AH PMON TSB FEBE Count (LSB) C04BH C14BH PMON TSB FEBE Count (MSB) C04CH C14CH PMON TSB CRC Count (LSB) C04DH C14DH PMON TSB CRC Count (MSB) C04EH C14EH PMON TSB LCV Count (LSB) C04FH C14FH PMON TSB LCV Count (MSB) C059H C159H RSLC TSB Configuration C05DH C15DH RSLC TSB Interrupt Enable/Status DOUT READ CYCLE WRITE CYCLE BALE BRWB BA[15:8] BAD[7:0] T1XC_WRB T1XC_RDB HCT245 DIR T1XC_CSB BE_CLOCK A[7:0] BA="C0"; BRWB=1 BA °"C0"; BRWB=1 BA="C0"; BRWB=0 BA °"C0"; BRWB=0 DOUT A[7:0] DIN A[7:0] DIN A[7:0] Figure 4: Decode Logic Waveforms 6.3 Clock PLL and DIP Switches One Mitel MT8940 provides all clocks necessary to drive the 2048 kbit/s backplane rate supported by the E1XC. The MT8940 is a dual digital PLL which can provide timing and synchronization signals for T1 or CEPT transmission links and the ST- BUS . The first PLL provides the T1 clock (1.544 MHz) synchronized to an input framing pulse. The second PLL provides CEPT or ST-BUS timing signals synchronized to an internal or external framing pulse signal. For a more detailed |
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