CS5560

DS713A5

11

7/31/07

VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%

Input levels: Logic 0 = 0V; Logic 1 = VD+; CL = 15 pF.

17. SDO will be high impedance when CS is high. In some systems it may require a pull-down resister.

Parameter

Symbol

Min

Typ

Max

Unit

Calibration Register Write Timing

Data setup time before SCLK rising

10

-

-

ns

Data hold time after SCLK rising

10

-

-

ns

SCLK rising to CS rising

10

-

-

ns

SCLK(i)

SDI

CS

LSB

MSB

LSB

MSB

Command Time

8 SCLKs

Data Time

24 SCLKs

Figure 5. SEC Mode - Write Timing (Not to Scale)