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PM7347 데이터시트(PDF) 67 Page - PMC-Sierra, Inc

부품명 PM7347
상세설명  SATURN USER NETWORK INTERFACE for J2/E3/T3
PDF  341 Pages
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제조업체  PMC [PMC-Sierra, Inc]
홈페이지  http://www.pmc-sierra.com
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PM7347 데이터시트(HTML) 67 Page - PMC-Sierra, Inc

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S/UNI®-JET Data Sheet
Released
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
67
Document ID: PMC-1990267, Issue 3
The RXCP-50 descrambles the cell payload field using the self synchronizing descrambler with a
polynomial of x43 + 1. The header portion of the cells can optionally be descrambled also. Note:
Cell payload scrambling is enabled by default in the S/UNI-JET as required by ITU-T
Recommendation I.432, but may be disabled to ensure backwards compatibility with older
equipment.
The HCS is a CRC-8 calculation over the first four octets of the ATM cell header. The RXCP-50
verifies the received HCS using the accumulation polynomial, x8 + x2 + x + 1. The coset
polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the received HCS octet before comparison
with the calculated result as required by the ATM Forum UNI specification, and ITU-T
Recommendation I.432.
The RXCP-50 can be programmed to drop all cells containing an HCS error or to filter cells
based on the HCS and the cell header. Filtering according to a particular HCS and the GFC, PTI,
and CLP bits of the ATM cell header is programmable through the RXCP-50 Registers. Note: The
VCI and VPI bits must be all logic zero. More precisely, filtering is performed when filtering is
enabled or when HCS errors are found when HCS checking is enabled. Otherwise, all cells are
passed on regardless of any error conditions. Cells can be blocked if the HCS pattern is invalid or
if the filtering 'Match Pattern' and 'Match Mask' Registers are programmed with a certain
blocking pattern. ATM Idle cells are filtered by default. For ATM cells, null or idle cells are
identified by the standardized header pattern of 'H00, 'H00, 'H00 and 'H01 in the first four octets
followed by the valid HCS octet.
While the cell delineation state machine is in the SYNC state, the HCS verification circuit
implements the state machine shown in Figure 7.



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