power disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass

capacitors to reject different frequencies of noise. The 0.1μF and 1μF capacitors are commonly used in parallel.

The bypass capacitor should be installed as close to the power terminal as possible for best results.

7.4 Layout

7.4.1 Layout Guidelines

• Bypass capacitor placement

– Place near the positive supply terminal of the device

– Provide an electrically short ground return path

– Use wide traces to minimize impedance

– Keep the device, capacitors, and traces on the same side of the board whenever possible

• Signal trace geometry

– 8mil to 12mil trace width

– Lengths less than 12cm to minimize transmission line effects

– Avoid 90° corners for signal traces

– Use an unbroken ground plane below signal traces

– Flood fill areas around signal traces

– For traces longer than 12cm

• Use impedance controlled traces

• Source-terminate using a series damping resistor near the output

• Avoid branches; buffer signals that must branch separately

7.4.2 Layout Example

W

W

≥ 5W

WORST

BETTER

BEST

Figure 7-3. Example Trace Corners for Improved Signal Integrity

CD54AC164, CD74AC164, CD54ACT164, CD74ACT164

SCHS240D – NOVEMBER 1998 – REVISED OCTOBER 2024

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14

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