7 Detailed Description

7.1 Overview

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with

each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may

be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift

register stage is transferred to the storage register when the Strobe input is high. Data in the storage register

appears at the outputs whenever the Output-Enable signal is high.

Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial

output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock

rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge,

provides a means for cascading these devices when the clock rise time is slow.

7.2 Functional Block Diagram

STR

OE

CP

DATA

D

Q

0

Q

1

Q

2

Q

D

Q

D

Q

D

Q

Q

3

Q

4

Q

5

Q

6

D

QS

1

Q

D

Q

Q

7

S

S

S

D

Q

QS

2

CD54HC4094, CD74HC4094, CD74HCT4094

SCHS211F – NOVEMBER 1997 – REVISED MARCH 2022

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