Data Sheet

ADIS16575/ADIS16576/ADIS16577

SPECIFICATIONS

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Table 7. Timing Specifications (Continued)

Parameter

Description

Normal Mode

Burst Read Mode

Unit

Min

Typ

Max

Min1

Typ

Max

tDAV

DOUT valid after SCLK edge

25

25

ns

tDSU

DIN setup time before SCLK rising edge

25

25

ns

tDHD

DIN hold time after SCLK rising edge

50

50

ns

tSCLKR, tSCLKF

SCLK rise and fall times

5

12.5

5

12.5

ns

tDR, tDF

DOUT rise and fall times

5

12.5

5

12.5

ns

tSFS

CS high after SCLK edge

0

0

ns

tSTDR

Input sync to data ready valid transition

240

µs

Direct sync mode, Register MSC_CTRL, Bits[3:2] = 01 (binary, see Table 120)

256

256

µs

tNV

Data invalid time

12

12

µs

t1

Input sync pulse width

5

5

µs

t2

Input sync period2

244

1/(Sync

Input Clock)

1/(Sync

Input Clock)

µs

1 N/A means not applicable.

2 This specification is rounded up from the cycle time that comes from the maximum input clock frequency (4100 Hz).

Timing Diagrams

Figure 2. SPI Timing and Sequence Diagram

Figure 3. Stall Time and Data Rate Timing Diagram

Figure 4. Input Clock Timing Diagram, External Sync Mode, Register MSC_CTRL, Bits[4:2] = 101 (Binary)