RM5231 datasheet(21/39 Pages) PMC

21 / 39 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

Document ID: PMC-2002165, Issue 1

RM5231™ Microprocessor with 32-bit System Bus Data Sheet

Released

significantly increases performance by decoupling the SysAD bus transfers from the instruction

execution stream.

3.21 System Interface

The system interface consists of a 32-bit Address/Data bus with 4 parity check bits and a 9-bit

command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is

capable of transferring data between the processor and memory at a peak rate of 400 MB/sec with

a 100 MHz SysClock.

Figure 6 shows a typical embedded system using the RM5231. In this example, a bank of DRAMs

and a memory controller ASIC share the processor’s SysAD bus while the memory controller

provides separate ports to a boot ROM and an I/O system.

Figure 6 Typical Embedded System Block Diagram

3.22 System Address/Data Bus

The 32-bit System Address Data (SysAD) bus is used to transfer addresses and data between the

RM5231 and the rest of the system. It is protected with a 4-bit parity check bus (SysADC).

The system interface is configurable to allow easy interfacing to memory and I/O systems of

varying frequencies. The Block Write data rate, Non-Block Write protocol, and Output Drive

Strength are programmable at Boot time via the Mode Control bits. The rate at which the

processor receives data is fully controlled by the external device.

3.23 System Command Bus

The RM5231 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates

whether the SysAD bus carries address or data information on a per-clock basis. If the SysAD

carries address, then the SysCmd bus also indicates what type of transaction is to take place (for

example, a read or write). If the SysAD carries data, then the SysCmd bus also gives information

about the data (for example, this is the last data word transmitted, or the data contains an error).

The SysCmd bus is bidirectional to support both processor requests and external requests to the

RM5231. Processor requests are initiated by the RM5231 and responded to by an external device.

External requests are issued by an external device and require the RM5231 to respond.

RM5231

Memory I/O

Controller

Flash/

Control

Boot

PCI Bus

Rom

Latch

DRAM

Address

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