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C

O

+

C

I

V

I

GND

MarginDown

L

O

A

D

Q2

+V

O

Q1

+

MarginUp

0V

+V

O

R

D

R

U

PT H12010W

( T opView)

1

2

10 9

8

7

6

5

4

3

GND

R

0.1W,1%

SET

PTH12030W/L

SLTS211F – MAY 2003 – REVISED FEBRUARY 2007

Table 6. Margin Up/Down Resistor Values

% ADJUST

5

0 k

Ω

4

24.9 k

Ω

3

66.5 k

Ω

2

150 k

Ω

1

397 k

Ω

Figure 20. Margin Up/Down Application Schematic

MARGIN UP/DOWN NOTES

1. The Margin Up and Margin Down controls were not intended to be activated simultaneously. If they are

their affects on the output voltage may not completely cancel, resulting in the possibility of a slightly

higher error in the output voltage set point.

2. The ground reference should be a direct connection to the module GND at pin 7 (pin 1 for the

PTHxx050). This will produce a more accurate adjustment at the load circuit terminals. The transistors Q1

and Q2 should be located close to the regulator.

3. The Margin Up and Margin Down control inputs are not compatible with devices that source voltage. This

includes TTL logic. These are analog inputs and should only be controlled with a true open-drain device

(preferably discrete MOSFET transistor). The device selected should have low off-state leakage current.

Each input sources 8 µA when grounded, and has an open-circuit voltage of 0.8 V.

20

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