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SC16C852LIB 데이터시트(PDF) 35 Page - NXP Semiconductors |
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SC16C852LIB 데이터시트(HTML) 35 Page - NXP Semiconductors |
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35 / 60 page ![]() SC16C852L_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 25 January 2007 35 of 60 NXP Semiconductors SC16C852L 1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder [1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer. 7.15 Transmit Interrupt Level Register (TXINTLVL) This 8-bit register is used to store the transmit FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. Table 27 shows TXINTLVL register bit settings. [1] For 32-byte FIFO mode, refer to Section 7.3. 7.16 Receive Interrupt Level Register (RXINTLVL) This 8-bit register is used to store the receive FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1. Table 28 shows RXINTLVL register bit settings. Table 26. Software flow control functions[1] Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls 0 0 X X No transmit flow control 1 0 X X Transmit Xon1/Xoff1 0 1 X X Transmit Xon2/Xoff2 1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2 X X 0 0 No receive flow control X X 1 0 Receiver compares Xon1/Xoff1 X X 0 1 Receiver compares Xon2/Xoff2 1011Transmit Xon1/Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 0111Transmit Xon2/Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1111Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 Table 27. TXINTLVL register bits description Bit Symbol Description 7:0 TXINTLVL[7:0] This register stores the programmable transmit interrupt trigger levels for 128-byte FIFO mode[1]. 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 Table 28. RXINTLVL register bits description Bit Symbol Description 7:0 RXINTLVL[7:0] This register stores the programmable receive interrupt trigger levels for 128-byte FIFO mode[1]. 0x00 = trigger level is set to 1 0x01 = trigger level is set to 1 ... 0x80 = trigger level is set to 128 |
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