CS42L51 datasheet(39/88 Pages) CIRRUS

39 / 88 page

DS679F1

CS42L51

4.5.1

Slave

LRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined based

on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will

then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-

alone control pin.

Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed

mode must be selected using the SPEED[1:0] bits.

4.5.2

Master

LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).

In Hardware Mode the CODEC operates in single-speed only. In Software Mode, the CODEC operates

in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.

Auto-Detect

QSM

HSM

SSM

DSM

Disabled

(Software

Mode only)

512, 768, 1024, 1536,

2048, 3072

256, 384, 512, 768,

1024, 1536

128, 192, 256, 384,

512, 768

128, 192, 256, 384

Enabled

1024, 1536, 2048*,

3072*

512, 768, 1024*, 1536*

256, 384, 512*, 768*

128, 192, 256*, 384*

*MCLKDIV2 must be enabled.

Table 3. MCLK/LRCK Ratios

÷ 256

÷ 128

÷ 512

LRCK Output

(Equal to Fs)

Single

Speed

Quarter

Speed

Half

Speed

SCLK Output

÷ 2

÷ 1

MCLK

MCLKDIV2

÷ 128

÷ 4

÷ 2

÷ 8

Single

Speed

Quarter

Speed

Half

Speed

÷ 2

Double

Speed

Double

Speed

SPEED[1:0]

Figure 17. Master Mode Timing

CS42L51 데이터시트(PDF) 39 Page - Cirrus Logic

CS42L51 데이터시트(HTML) 39 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

데이터시트 다운로드

링크 URL