VDD

VDD

GND

1 MHz

Capacitance

Meter

Capacitance is measured at SX, DX,

and logic pins during ON and OFF

conditions

S1A

D1

S1B

S4A

D4

S4B

SEL

LOGIC CONTROL

EN

VOUT

Output

VS

0 V

VDD

QC = CL ×

VOUT

VEN

GND

OUTPUT

CL

D1

VDD

VDD

0.1 F

VOUT

VEN

VS

S1A

S1B

OUTPUT

CL

D4

VOUT

VS

S4A

S4B

EN

19

TMUX1574

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SCDS391C – OCTOBER 2018 – REVISED DECEMBER 2019

Product Folder Links: TMUX1574

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7.11 Charge Injection

The amount of charge injected into the source or drain of the device during the falling or rising edge of the gate

signal is known as charge injection, and is denoted by the symbol QC. Figure 37 shows the setup used to

measure charge injection from source (Sx) to drain (Dx).

Figure 37. Charge-Injection Measurement Setup

7.12 Capacitance

The parasitic capacitance of the device is captured at the source (Sx), drain (Dx), and select (SELx) pins. The

capacitance is measured in both the on and off state and is denoted by the symbol CON and COFF. Figure 38

shows the setup used to measure capacitance.

Figure 38. Capacitance Measurement Setup