ST72F321AR datasheet(160/189 Pages) STMICROELECTRONICS

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ST72321

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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 89. RESET pin protection when LVD is enabled.1)2)3)4)5)

Figure 90. RESET pin protection when LVD is disabled.1)2)3)

1. The reset network protects the device against parasitic resets.

2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in Section 12.9.1. Otherwise the reset will not be taken into account internally.

4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value

specified for IINJ(RESET) in section 12.2.2 on page 139.

5. When the LVD is enabled, it is mandatory not to connect a pull-up resistor and a capacitor to VDD on the RESET pin.

0.01

µF

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

WATCHDOG

LVD RESET

INTERNAL

RESET

EXTERNAL

Recommended

0.01

µF

VDD

0.01

µF

EXTERNAL

RESET

CIRCUIT

USER

VDD

4.7k

Ω

Required

Recommended

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

WATCHDOG

INTERNAL

RESET

ST72F321AR 데이터시트(PDF) 160 Page - STMicroelectronics

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