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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72F321AR 데이터시트(PDF) 47 Page - STMicroelectronics |
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ST72F321AR 데이터시트(HTML) 47 Page - STMicroelectronics |
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47 / 189 page  ST72321 47/189 I/O PORTS (Cont’d) Figure 31. I/O Port General Block Diagram Table 9. I/O Port Mode Options Legend: NI - not implemented Off - implemented not activated On - implemented and activated Note: The diode to VDD is not implemented in the true open drain pads. A local protection between the pad and VSS is implemented to protect the de- vice against positive stress. Configuration Mode Pull-Up P-Buffer Diodes to VDD to VSS Input Floating with/without Interrupt Off Off On On Pull-up with/without Interrupt On Output Push-pull Off On Open Drain (logic level) Off True Open Drain NI NI NI (see note) DR DDR OR PAD VDD ALTERNATE ENABLE ALTERNATE OUTPUT 1 0 OR SEL DDR SEL DR SEL PULL-UP CONDITION P-BUFFER (see table below) N-BUFFER PULL-UP (see table below) 1 0 ANALOG INPUT If implemented ALTERNATE INPUT VDD DIODES (see table below) EXTERNAL SOURCE (eix) INTERRUPT CMOS SCHMITT TRIGGER REGISTER ACCESS |
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