AL4V95 datasheet(2/2 Pages) AVERLOGIC

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AVERLOGIC TECHNOLOGIES, INC.

TEL

: 1 408 361-0400

e-mail: sales_usa@averlogic.com URL: www.averlogic.com

AVERLOGIC TECHNOLOGIES, CORP. TEL: 886 2-87523988 e-mail: sales@averlogic.com.tw URL: www.averlogic.com.tw

October 30, 2004

(2k, 8k) x9

Memory

Array

Input

Buffer

Output

Buffer

Write

Control

Logic

Read

Control

Logic

Timing & Logic

Control

Write Pointer

Read Pointer

Offset

Regissers

Input data bus

Output data bus

/OE

WCLK

/WEN

RCLK

/REN

AL4V9x FIFO Block Diagram

/WRST

/RRST

The 9-bit input and output ports operate

independently at

maximum

speed

100MHz. The built-in address decoder and

pointer

managing

circuits

provide

straightforward

bus

interface

serially

read/write memory that reduces inter-chip

design

efforts.

The

AL4V9x

embedded

memory array and high performance process

technologies

with

extended

controller

functions (read skip, fixed and programmable

status flags... etc.) offer flexible memory

management.

The input data is synchronous with a free-

running clock (WCLK), and input-enable pins

(/WEN). Data is written into the FIFO on

every clock when enable pins are asserted.

The output is synchronous with the other free-

running clock (RCLK) and enables (/REN).

An Output Enable pin (/OE) is provided at the

read port for tri-state control of the output port.

The AL4V9x series are operating in 3.3V

power supply with 5V signal tolerant input.

These chips are available as a 32-pin TQFP

Package.

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