LT7184SRVPBF datasheet(37/52 Pages) AD

37 / 52 page

Data Sheet

LT7184S

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Rev. 0

37 of 52

CITH, can be adjusted in 10pF increments from 95pF to 165pF (typical) using the MFR_PWM_MODE_LT7184S bits [8:6],

as shown in Table 15.

Figure 37. External Compensation

Figure 38. Programmable Internal Compensation

Control Loop Model

An equivalent circuit model for the LT7184S regulator is shown in Figure 39. The error amplifier is a transconductance

amplifier with finite output impedance and programmable gain (REA and gMEA as shown in Table 13). The error

amplifier's input capacitance of about 220fF forms a parasitic pole with the input feedback divider with Thevenin

equivalent resistance of about 24kΩ. The power section, consisting of the modulator, power switches current sense,

and inductor is modeled as an RC network with a bandwidth of about 13MHz (RMOD, CMOD) followed by a

transconductance amplifier, gM(MOD), see Table 12. The output capacitor, COUT, integrates this current, and the

capacitance on the ITH node (CITH, if internal, see Table 15) integrates the error amplifier output current, resulting in

two dominant poles in the loop. A zero is required and comes from resistor RITH (if internal, see Table 14) in series with

CITH. This simple model works well if the inductor value is not too high and the loop crossover frequency is much

lower than the switching frequency, fSW. When modeling PolyPhase applications, the error amplifiers are summed

together, and the ITHN nodes must be connected to a single external compensation network. When using external

compensation networks, care must be taken with the layout of the external ITH network to limit the capacitance to

ground CPARA.

Figure 39.Control Loop Model

INTVCC

LT7184S

ITH

I =

gMEA × (VREF – VSENSE)

VSENSEP

VREF

RITH

CITH

VSENSEN

VSENSE = VSENSEP – VSENSEN

SGND

–

ERROR

AMP

(EA)

INT

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