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MB95F128MB 데이터시트(PDF) 59 Page - fujitsu semiconductor

부품명 MB95F128MB
상세설명  8-bit Microcontrollers
PDF  80 Pages
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제조업체  FUJITSU [fujitsu semiconductor]
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MB95F128MB 데이터시트(HTML) 59 Page - fujitsu semiconductor

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MB95120MB Series
59
(VCC
= 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to + 105 °C)
(Continued)
Parameter
Sym-
bol
Pin
name
Condition
Value*2
Unit
Remarks
Min
Max
SCL clock
“L” width
tLOW
SCL0
R
= 1.7 kΩ,
C
= 50 pF*1
(2
+ nm / 2) tMCLK − 20
⎯
ns
Master mode
SCL clock
“H” width
tHIGH
SCL0
(nm
/ 2) tMCLK − 20
(nm
/ 2 ) tMCLK + 20
ns
Master mode
Start condition
hold time
tHD;STA
SCL0
SDA0
(
−1 + nm / 2) tMCLK − 20
(
−1 + nm) tMCLK + 20
ns
Master mode
Maximum value is
applied when m,
n
= 1, 8.
Otherwise, the
minimum value is
applied.
Stop condition
setup time
tSU;STO
SCL0
SDA0
(1
+ nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition
setup time
tSU;STA
SCL0
SDA0
(1
+ nm / 2) tMCLK − 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Bus free time
between stop
condition and
start condition
tBUF
SCL0
SDA0
(2 nm
+ 4) tMCLK − 20
⎯
ns
Data hold time tHD;DAT
SCL0
SDA0
3 tMCLK
− 20
⎯
ns
Master mode
Data setup
time
tSU;DAT
SCL0
SDA0
(
−2 + nm / 2) tMCLK − 20 (−1 + nm / 2) tMCLK + 20 ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit
of continuous
data.
Otherwise,
the maximum
value is applied.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT SCL0
(nm
/ 2) tMCLK − 20
(1 + nm
/ 2) tMCLK + 20
ns
Minimum value is
applied to interrupt
at 9th SCL
↓.
Maximum value is
applied to interrupt
at 8th SCL
↓.
SCL clock “L”
width
tLOW
SCL0
4 tMCLK
− 20
⎯
ns
At reception
SCL clock “H”
width
tHIGH
SCL0
4 tMCLK
− 20
⎯
ns
At reception
Start condition
detection
tHD;STA
SCL0
SDA0
2 tMCLK
− 20
⎯
ns
Undetected when
1 tMCLK is used at
reception



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