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PPC405GPR-3JB266 데이터시트(PDF) 45 Page - Applied Micro Circuits Corporation

부품명 PPC405GPR-3JB266
상세설명  Power PC 405GPr Embedded Processor
PDF  57 Pages
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제조업체  AMCC [Applied Micro Circuits Corporation]
홈페이지  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

PPC405GPR-3JB266 데이터시트(HTML) 45 Page - Applied Micro Circuits Corporation

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405GPr – Power PC 405GPr Embedded Processor
AMCC
45
Revision 2.04 – September 7, 2007
Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
Max
Units
PCIClk input frequency (asynchronous mode)
Note 1
66.66
MHz
PCIClk period (asynchronous mode)
15
Note 1
ns
PCI Clock frequency (synchronous mode)
25
33.33
MHz
PCI Clock period (synchronous mode - Note 2)
30
40
ns
PCIClk input high time
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
–
2.5
MHz
EMCMDClk period
400
–
ns
EMCMDClk output high time
160
–
ns
EMCMDClk output low time
160
–
ns
PHYTxClk input frequency
2.5
25
MHz
PHYTxClk period
40
400
ns
PHYTxClk input high time
35% of nominal period
–
ns
PHYTxClk input low time
35% of nominal period
–
ns
PHYRxClk input frequency
2.5
25
MHz
PHYRxClk period
40
400
ns
PHYRxClk input high time
35% of nominal period
–
ns
PHYRxClk input low time
35% of nominal period
–
ns
PerClk output frequency
–
66.66
MHz
PerClk period
15
–
ns
PerClk output high time
45% of nominal period
55% of nominal period
ns
PerClk output low time
45% of nominal period
55% of nominal period
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
± 0.3
ns
UARTSerClk input frequency (Note 3)
–
1000/(2TOPB+2ns)
MHz
UARTSerClk period
2TOPB+2
–ns
UARTSerClk input high time
TOPB+1
–ns
UARTSerClk input low time
TOPB+1
–ns
TmrClk input frequency
–
66.66
MHz
TmrClk period
15
–
ns
TmrClk input high time
40% of nominal period
60% of nominal period
ns
TmrClk input low time
40% of nominal period
60% of nominal period
ns
Note:
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GPr Embedded Processor
User’s Manual for more information.
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. TOPB is the period in ns of the OPB clock. The maximum OPB clock frequency is 66.66MHz.



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