PPC440EP-3PBFFFCX datasheet(13/84 Pages) AMCC

13 / 84 page

AMCC Proprietary

440EP – PPC440EP Embedded Processor

Data Sheet

Revision 1.26 – April 25, 2007

DMA to PLB 128 Controller

This DMA controller provides a DMA interface dedicated to the USB 2.0 device ports and the 128-bit PLB.

Features include:

• 4 independent channels supporting internal USB 2.0 Device endpoints 1 and 2

• Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers

• Scatter/gather capability

• 128-byte buffer with programmable thresholds

Serial Ports (UART)

Features include:

• Up to four ports in the following combinations:

– One 8-pin

– Two 4-pin

– One 4-pin and two 2-pin

– Four 2-pin

• Selectable internal or external serial clock to allow wide range of baud rates

• Register compatibility with NS16750 register set

• Complete status reporting capability

• Fully programmable serial-interface characteristics

• Supports DMA using internal DMA function on PLB 64

IIC Bus Interface

Features include:

• Two IIC interfaces provided

• Support for Philips® Semiconductors I2C Specification, dated 1995

• Operation at 100kHz or 400kHz

•8-bit data

• 10- or 7-bit address

• Slave transmitter and receiver

• Master transmitter and receiver

• Multiple bus masters

• Supports fixed VDD IIC interface

• Two independent 4 x 1 byte data buffers

• Twelve memory-mapped, fully programmable configuration registers

• One programmable interrupt request signal

• Provides full management of all IIC bus protocols

• Programmable error recovery

• Includes an integrated boot-strap controller that is multiplexed with the second IIC interface

PPC440EP-3PBFFFCX 데이터시트(PDF) 13 Page - Applied Micro Circuits Corporation