CAT25010LET3 datasheet(6/17 Pages) CATALYST

6 / 17 page

CAT25010, CAT25020, CAT25040

Doc. No. MD-1006 Rev. T

Characteristics subject to change without notice

WRITE OPERATIONS

The CAT25010/20/40 device powers up into a write

disable state. The device contains a Write Enable

Latch (WEL) which must be set before attempting to

write to the memory array or to the status register. In

addition, the address of the memory location(s) to be

written must be outside the protected area, as defined

by BP0 and BP1 bits from the status register.

Write Enable and Write Disable

The internal Write Enable Latch and the corresponding

Status Register WEL bit are set by sending the WREN

instruction to the CAT25010/20/40. Care must be taken

to take the CS

¯¯ input high after the WREN instruction,

as otherwise the Write Enable Latch will not be

properly set. WREN timing is illustrated in Figure 2.

The WREN instruction must be sent prior any WRITE

or WRSR instruction.

The internal write enable latch is reset by sending the

WRDI instruction as shown in Figure 3. Disabling write

operations by resetting the WEL bit, will protect the

device against inadvertent writes.

Figure 2. WREN Timing

Note:

Dashed Line = mode (1, 1) - - - - - -

Figure 3. WRDI Timing

Note:

Dashed Line = mode (1, 1) - - - - - -

SCK

000

HIGH IMPEDANCE

SCK

000

HIGH IMPEDANCE

CAT25010LET3 데이터시트(PDF) 6 Page - Catalyst Semiconductor