Functional Description

Operation

The 3

HT600/HT680 or D12~D15 for the HT6207, active high). This cycle will repeat itself as long as the transmission enable

(TE or D12~D15) is held high. Once the transmission enable falls low, the encoder output completes its final cycle and

then stops as shown below.

Information Word

An information word consists of four periods as shown:

Address/Data Waveform

Each programmable address/data pin can be externally set to one of the following three logic states:

The

²Open² state data input is interpreted as logic low by the decoders since the decoder output only have two states.

Address/Data Programming (Preset)

The status of each address/data pin can be individually preset to logic

²high², ²low²,or ²floating². If a transmission en-

able signal is applied, the encoder scans and transmits the status of the 18 bits of address/data serially in the order A0

to AD17 for the HT600/HT680 and A0 to D15 for the HT6207.

There are some packaging limitations. For example t he 18-pin DIP HT680, offers four external data bits and eight ex-

ternal address bits. The remaining unpackaged bits or dummy codes are treated as floating for A0~AD17 or as pull-low

for D12~D15. During an information transmission these bits are still located in their original position. But if the trigger

signal is not applied, the chip only consumes a standby current which is less than 1

mA.

HT600/HT680/HT6207

Rev. 1.10

5

January 24, 2003

3 w o r d s

3 w o r d s

E n c o d e r

D a t a O u t

T r a n s m i t t e d

C o n t i n u o u s l y

< 1 w o r d

T E o r

D 1 2 ~ D 1 5

Transmission timing

P i l o t p e r i o d

( 6 b i t s )

A d d r e s s c o d e p e r i o d

D a t a c o d e p e r i o d

1 / 6 b i t

S y n c . p e r i o d

Composition of information

" O n e "

" Z e r o "

" O p e n "

A d d r e s s / D a t a B i t

f o s c ¸ 3 3

Address/Data bit waveform