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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HT45RM03 데이터시트(PDF) 14 Page - Holtek Semiconductor Inc |
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HT45RM03 데이터시트(HTML) 14 Page - Holtek Semiconductor Inc |
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14 / 54 page  HT45RM03 Rev. 1.10 14 February 16, 2007 An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). Program Counter 000H Interrupt Disable WDT Clear. After master reset, WDT begins counting Timer/Event Counter Off Input/Output Ports Input mode Stack Pointer Points to the top of the stack The registers states are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Program Counter 000H 000H 000H 000H 000H TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu TMR1C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PC 0011 1111 0011 1111 0011 1111 0011 1111 uuuu uuuu PCC --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu PD ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u PDC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u PWMH 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu PWML ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu PWMC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu MISC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL x--- ---- x--- ---- x--- ---- x--- ---- u--- ---- ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu CMPC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu OPAC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu Note: ²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown |
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