5

 2006 Semtech Corp.

www.semtech.com

SC4602A/B

POWER MANAGEMENT

Ordering Information

Pin Descriptions

r

e

b

m

u

N

t

r

a

P

)

1

(

z

H

ke

c

i

v

e

D

R

T

S

M

I

A

2

0

6

4

C

S

0

0

38

-

P

O

S

M

T

R

T

S

M

I

A

2

0

6

4

C

S

)

2

(

R

T

S

M

I

B

2

0

6

4

C

S

0

5

58

-

P

O

S

M

T

R

T

S

M

I

B

2

0

6

4

C

S

)

2

(

B

V

E

A

2

0

6

4

C

S

d

r

a

o

B

n

o

it

a

u

l

a

v

E

B

V

E

B

2

0

6

4

C

S

VCC: Positive supply rail for the IC. Bypass this pin to

GND with a 0.1 to 4.7µF low ESL/ESR ceramic capaci-

tor.

GND: All voltages are measured with respect to this pin.

All bypass and timing capacitors connected to GND should

have leads as short and direct as possible.

SYNC/SLEEP: The oscillator of SC4602A and SC4602B

are set to 300kHz and 550kHz respectively when SYNC/

SLEEP is pulled and held above 2V. Synchronous mode

operation is activated as the SYNC/SLEEP is driven by an

external clock. The oscillator and PWM are designed to

provide practical operation to 450kHz for SC4602A and

to 700kHz for SC4602B when synchronized. Sleep mode

is invoked if SYNC/SLEEP is pulled and held below 0.8V

which can be accomplished by an external gate or tran-

sistor. Sleepmode supply current is 10µA typical.

VSENSE: This pin is the inverting input of the voltage

amplifier and serves as the output voltage feedback point

for the Buck converter. It senses the output voltage through

an external divider.

COMP: This is the output of the voltage amplifier. The

voltage at this output is inverted internally and connected

to the non-inverting input of the PWM comparator. A lead-

lag network around the voltage amplifier compensates for

the two pole LC filter characteristic inherent to voltage mode

control and is required in order to optimize the dynamic

performance of the voltage mode control loop.

PHASE: This input is connected to the junction between

the two external power MOSFET transistors. The voltage

drop across the upper P-channel device is monitored by

PHASE during conduction and forms the current limit

comparator. Logic sets the PWM latch and terminates

the output pulse. The controller stops switching and goes

through a soft start sequence once the converter out-

put voltage drops below 68.75% its nominal voltage. This

prevents excess power dissipation in the PMOSFET dur-

ing a short circuit. The reverse current comparator senses

the drop across the lower N-channel MOSFET during its

conduction and disables the drive signal if a small posi-

tive voltage is present. To disable the overcurrent com-

parator, connect PHASE to VCC.

PDRV, NDRV: The PWM circuitry provides complemen-

tary drive signals to the output stages. Cross conduc-

tion of the external MOSFETS is prevented by monitoring

the voltage on the P-channel and N-channel driver pins

in conjunction with a time delay optimized for FET turn-

off characteristics.

(8 Pin MSOP)

Notes:

(1) Only available in tape and reel packaging. A reel

contains 2500 devices.

(2) Lead free product. This product is fully WEEE and

RoHS compliant.

Pin Configuration

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