| 전자부품 데이터시트 검색엔진 |
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SH3100 데이터시트(PDF) 73 Page - Semtech Corporation |
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SH3100 데이터시트(HTML) 73 Page - Semtech Corporation |
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73 / 80 page ![]() SH3100 POWER MANAGEMENT 73 © 2006 Semtech Corp. www.semtech.com SA 2 SA 0 SA 1 Slave address (3 LSBs determined by I2CSlaveAddr register) R/ W RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Register Address SA 2 SA 0 SA 1 0 Slave address (3 LSBs determined by I2CSlaveAddr register) R/ W WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 WD 0 Write Data Write to single register (combined format) SAn = Slave Address (bit n) RAn = Register Address (bit n) WDn = Write Data (bit n) RDn = Read Data (bit n) SCL may be briefly held low (stretched) by SH3100 here SA2 SA0 SA1 Slave address (3 LSBs determined by I2CSlaveAddr register) R/W RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 Register Address WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Write Data Write to single register ('normal' format) SCL may be briefly held low (stretched) by SH3100 here SDA and SCL are driven by the Master unless otherwise specified. Read from single register (combined format) SA 2 SA 0 SA 1 Slave address (3 LSBs determined by I2CSlaveAddr register) R/ W RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Register Address SA 2 SA 0 SA 1 Slave address (3 LSBs determined by I2CSlaveAddr register) R/ W RD 7 RD 6 RD 5 RD 4 RD 3 RD 2 RD 1 RD 0 Read data driven by SH3100 SCL may be briefly held low (stretched) by SH3100 here SCL SDA SCL SDA SCL SDA I2C Timing Diagrams Functional Descriptions (continued) |
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