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 2003 Semtech Corp.

www.semtech.com

SC1480A

POWER MANAGEMENT

Application Information (Cont.)

Layout Guidelines

One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and

maximize heat dissipation. The IC ground reference, VSSA, should be kept separate from power ground. All

components that are referenced to VSSA should connect to it locally at the chip. VSSA should connect to power

ground at the output capacitor(s) only.

.eedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.

Route the feedback trace with VSSA as a differential pair from the output capacitor back to the chip. Run them in

a “quiet layer” if possible.

Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins (VDDP and PGND, VCCA and VSSA) and

connected directly to them on the same side.

Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling

(including the chip power ground connections). Power components should be placed to minimize loops and reduce

losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use

“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of

the MOS.ETs to reduce parasitic impedances (and MOS.ET switching losses), the low-side MOS.ET is most critical.

Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling

requirement (and to reduce parasitics) if routed on more than one layer

Current sense connections must always be made using Kelvin connections to ensure an accurate signal.

We will examine the SC1480A DDR2 reference design used in the Design Procedure section while explaining the

layout guidelines in more detail.

4

1

2

3

5

6

7

8

Q1

FDS6982S

C3

0u1

C1

10u

0402

0402

0603

0402

0402

0402

0402

0402

0402

0402

7343

1210

0603

0402

0402

0603

SOD323

0603

2525

R8

0R

0402

REFIN

1

TON

2

REFOUT

3

VCCA

4

FB

5

PGD

6

VSSA

7

PGND

8

DL

9

VDDP

10

ILIM

11

LX

12

DH

13

BST

14

U1

SC1480A

C9

1u

C8

1n

R7

10R

R4

10R

R3

470k

R2

715k

R1

10k0

R6

10k0

VTT

VBAT

VDDQ

5VSUS

PGOOD

C2

1u

REFOUT

C10

1u

R5

9k09

D1

C5

0u1

5VRUN

C4

2n2

VBAT

L1

2u2

+

C6

220u/15mOhm

VTT

C7

0u1

.igure 3: Reference Design and Layout Example for VBAT = 8V to 20V, VTT = 0.9V, 3A

Note R8 is present to facilitate isolation of power ground and VSSA during layout.