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 2005 Semtech Corp.

www.semtech.com

SC4901

POWER MANAGEMENT

Layout Guidelines

The Combi Sync topology and SC4901 are intended for

use in multi output convertors and demand careful

attention to good layout practices. The topology has an

inherent advantage in that all switching circuits naturally

operate at the same frequency set by the primary controller.

But the operating duty ratio is different for different outputs

and this may cause unexpected interferences. Make sure

that the currents in the RTN path are kept separate and

returned to a single node at the transformer end. High

current returns from one output should be isolated from

the signal current returns going into the AGND pins of other

outputs.

A dedicated ground plane is strongly

recommended to improve noise immunity.

SC4901 requires a clean synchronising signal at the ZCD

pin to ensure proper operation. There are several sources

that may contribute to the noise at this pin. The traces

from the transformer terminals to the corresponding QS

drain and QR source pins must be kept to the absolute

minimum. When the FETs are turned ON or OFF, the current

in the transformer secondary winding is subjected to a rapid

rate of di/dt. Long traces that encompass wide areas have

higher parasitic lead inductances. The combination of a

rapid di/dt and large parasitic inductance is a dip or spike

in the transformer waveform which can confuse the ZCD

pin and lead to random transitions at the output. The series

resistor RZ shown in the Typical Application Circuit should

have a separate connection to the transformer secondary

terminal where the source waveform is relatively free of

distortions.

The primary side layout also requires special attention.

Excessive ringing or spikes on the primary side will be

reflected to the secondary and interfere with the controller

operation. It is important to physically separate the primary

and secondary circuits and use separate ground planes to

minimise interference.

The drive transformer for the forward FETs can contribute

significantly to the overall performance. For fast rise and

fall times and low switching losses, choose a driver with

low inductances. The traces from the transformer to OUTA

and XFRA pins must be kept short to minimise the overall

inductance in the drive path.

Application Information (Cont.)

Reference Design and Typical Waveforms

The complete schematic of a secondary channel delivering

3.3V/10A is shown in Fig 4). Typical waveforms are shown

in Figs 5) to Fig 8) These waveforms were taken on a dual

output convertor with 48V input and a transformer turns

ratio of 6:1. Both outputs were generated off a single

secondary winding. The primary topology was a free

running, active reset, forward convertor operating at 225

kHz. Volt second control was implemented using input

feedforward with a maximum duty ratio of 65% at 40V

input. The two outputs were rated at 3.3V/13A and 2.5V/

13A for a total of 75W power. Of special interest are the

primary side waveforms shown in Fig 8). The zero current

turn on can be clearly seen. During turn off, the current

decreases as 2.5V forward FETs turn off first, followed by

3.3V output. The last small step at final turn off represents

the magnetising current in transformer primary.