9

 2007 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC2621A

Applications Information (Cont.)

100

1K

10K

100K

1M

-60

-30

0

30

60

Fo

Fz

Fz1

Fz2

Fp1

Fp2

Fc

FR EQ UENCY (Hz )

COM PENSATOR GAI N

CON

VERT

ER G

AIN

LOO

P GA

IN

100

1K

10K

100K

1M

-60

-30

0

30

60

Fo

Fz

Fz1

Fz2

Fp1

Fp2

Fc

FR EQ UENCY (Hz )

COM PENSATOR GAI N

CON

VERT

ER G

AIN

LOO

P GA

IN

Fig. 4. Bode plots for control loop design

Rbot

Vo

C1

VREF

0.5V

R2

R3

Rtop

3

2

1

C2

C3

Vc

Fig. 5. Compensation network

is found from:

top

O

bot

R

V

V

V

R

×

-

=

5

.

0

5

.

0

where 0.5V is the internal reference voltage of the

SC2621A.

The other components of the compensator can be cal-

culated using following design procedure:

(1). Plot the converter gain, including LC filter and PWM

modulator.

(2). Select the open loop crossover frequency Fc located

at 10% to 20% of the switching frequency. At Fc, find the

required DC gain.

(3). Use the first compensator pole Fp1 to cancel the

ESR zero Fz.

(4). Have the second compensator pole Fp2 at half the

switching frequency to attenuate the switching ripple and

high frequency noise.

(5). Place the first compensator zero Fz1 at or below

50% of the power stage resonant frequency Fo.

(6). Place the second compensator zero Fz2 at or below

the power stage resonant frequency Fo.

A MathCAD program is available upon request for the

calculation of the compensation parameters.

LA

LA

LA

LA

LAYYYYYOUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

The switching regulator is a high di/dt power circuit. Its

Printed Circuit Board (PCB) layout is critical. A good lay-

out can achieve an optimum circuit performance while

minimizing the component stress, resulting in better sys-

tem reliability. During PCB layout, the SC2621A control-

ler, MOSFETs, inductor, and power decoupling capacitors

have to be considered as a unit.

The following guidelines are typically recommended for

using the SC2621A controller.

(1). Place a 4.7uF to 10uF ceramic capacitor close to

the drain of top MOSFET for the high frequency and high

current decoupling. The loop formed by the capacitor,

the top and bottom MOSFETs must be as small as pos-

sible. Keep the input bulk capacitors close to the drain

of the top MOSFETs.

(2). Place the SC2621A over a quiet ground plane to avoid

pulsing current noise. Keep the ground return of the gate

drive short.

(3). Connect bypass capacitors as close as possible to

the decoupling pins (DRV and Vcc) to the ground pin GND.

The trace length of the decoupling capasitor on DRV pin

should be no more than 0.2” (5mm).

(4). Locate the components of the bootstrap circuit close

to the SC2621A.