19

 2005 Semtech Corp.

www.semtech.com

SC470

POWER MANAGEMENT

As shown below, VOUT and VSSA should be routed as a differential pair to the output capacitor(s).

C11

1uF

R4

20k0

R8

20k0

EN/PSV

1

TON

2

VOUT

3

VCCA

4

FB

5

PGD

6

VSSA

7

PGND

8

DL

9

VDDP

10

ILIM

11

LX

12

DH

13

BST

14

U2

SC470

VOUT

+

C7

220u/25m

VOUT

0402

0402

C6

56p

0402

0603

R12 0R (2)

7343

0402

+

C14

220u/25m

7343

VOUT

VOUT

VSSA

Figure 11: Differential Routing of Feedback and Ground Reference Traces

Next, the schematic in Figure 12 below shows the power section. The highest di/dts occur in the input loop (highlighted

in red) and thus this loop should be kept as small as possible.

Q1

IRF7811AV

Q2

FDS6676S

C2

2n2/50V

VBAT

L1

2u2

+

C7

220u/25m

VOUT

R6 0R (2)

7343

0402

+

C6

220u/25m

7343

0402

C3

0u1/25V

C4

10u/25V

1210

0603

Figure 12: Power Section and Input Loop

The input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce EMI. Use

large copper pours to minimize losses and parasitics. See Figure 13 on Page 20 for an example.

Application Information (Cont.)