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SC339EVB 데이터시트(PDF) 8 Page - Semtech Corporation

부품명 SC339EVB
상세설명  Ultra Low Output Voltage Linear FET Controller
PDF  15 Pages
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제조업체  SEMTECH [Semtech Corporation]
홈페이지  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC339EVB 데이터시트(HTML) 8 Page - Semtech Corporation

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© 2006 Semtech Corp.
www.semtech.com
SC339
PRELIMINARY
POWER MANAGEMENT
Table 1 lists recommended resistor values for some stan-
dard output voltages. All resistors are 1%, 1/10W.
The maximum output voltage that can be obtained
from each output is determined by the input supply
voltage and the R
DS(ON) and gate threshold voltage of the
external MOSFET. Assuming that the MOSFET gate
threshold voltage is sufficiently low for the output
voltage chosen and the worst-case drive voltage, V
OUT(MAX)
is given by:
V
OUT (MAX) = VDRAIN(MIN) ― IOUT(MAX) • RDSON(MAX)
Recommended Resistor Values For SC339
Design Example
Goal: 1.05V±5% @ up to 2.5A from 1.2V±5% and 5V±5%
Solution 1: No Passive Droop
Total window for DC error, ripple and transient is
±52.5mV.
Since this device is linear and assuming that it has been
designed to not ever enter dropout, there is negligible ripple
on the output.
The DC error for this output is the sum of:
V
ADJ accuracy = ±1% = ±10.5mV
Feedback chain tolerance = ±1% = ±10.5mV
Load regulation = ±0.25% = ±2.6mV
Resistors per Table 1 should be 11.0k
Ω (top) and 10.0kΩ
(bottom).
V
OUT (V)
R1 or R3 (kΩ)
R2 or R4 (kΩ)
1.05
11.0
10.0
1.2
14.0
10.0
1.5
20.0
10.0
2.5
45.3
11.3
3.3
63.4
11.3
Applications Information (Cont.)
Total DC error = ±2.25% = 23.6mV
This leaves ±2.75% = 28.875mV for the load transient ESR
spike, therefore:
28.875mV
R
ESR(MAX) =
—————— =
11.55m
Ω
2.5A
Bulk capacitance required is given by:
dl •
τ
C
BULK(MIN) = ——— = μF
dV
Where dI is the maximum load current step, t is the
maximum regulator response time and dV is the
allowable voltage droop. Therefore with dI = 2.5A,
t = 1μs, and dV = 28.875mV:
2.5 • 1 • 10¯
6
C
BULK(MIN) = ———————— = 87μF
28.875
• 10¯
3
So if we use 1% V
OUT set resistors we would select
100μF, 12m
Ω POSCAP for output capacitance (which
assumes that local ceramic bypass capacitors will
absorb the balance of the (12 - 11.55)m
Ω ESR
requirement - otherwise 10m
Ω capacitors should be
used).
If we use 0.1% set resistors, then the total DC error
becomes ±1.35% = ±15.75mV, leaving ±3.65% = 38.33mV
for the ESR spike. In this case:
38.33mV
R
ESR(MAX) =
———— =
15.33m
Ω and,
2.5A
=
2.5 • 1 • 10¯
6
C
BULK(MIN)
——————— = 65
μF
38.33 • 10¯3
So for 0.1% resistors we could use 1 x 100μF, 15m
Ω
POSCAP for output capacitance.



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