Pad Coordinates

Unit: mil

Pad No.

X

Y

Pad No.

X

Y

1

-55.04

59.46

25

58.14

-25.29

2

-58.52

22.18

26

58.14

-18.66

3

-58.52

15.56

27

58.14

-11.94

4

-58.52

5.36

28

58.14

-5.31

5

-58.52

-4.51

29

58.14

1.32

6

-58.52

-11.14

30

58.14

7.95

7

-58.52

-34.76

31

58.14

14.58

8

-58.52

-41.90

32

58.14

21.21

9

-58.52

-49.13

33

55.55

59.46

10

-58.52

-59.08

34

48.92

59.46

11

-44.07

-59.08

35

42.29

59.46

12

-31.58

-59.08

36

35.66

59.46

13

-20.70

-59.08

37

29.03

59.46

14

-13.98

-59.08

38

22.40

59.46

15

-7.05

-59.08

39

15.77

59.46

16

-0.34

-59.08

40

9.14

59.46

17

6.33

-59.08

41

2.42

59.46

18

12.96

-59.08

42

-4.21

59.46

19

19.59

-59.08

43

-10.84

59.46

20

58.14

-58.44

44

-17.47

59.46

21

58.14

-51.81

45

-24.10

59.46

22

58.14

-45.18

46

-30.73

59.46

23

58.14

-38.55

47

-38.17

59.46

24

58.14

-31.92

48

-45.39

59.46

Pad Description

Pad No.

Pad Name

I/O

Function

1CS

I

Chip selection input with pull-high resistor

When the CS is logic high, the data and command read from or written to

the HT1621 are disabled. The serial interface circuit is also reset. But if CS

is at logic low level and is input to the CS pad, the data and command trans-

mission between the host controller and the HT1621 are all enabled.

2RD

I

READ clock input with pull-high resistor

Data in the RAM of the HT1621 are clocked out on the falling edge of the RD

signal. The clocked out data will appear on the DATA line. The host control-

ler can use the next rising edge to latch the clocked out data.

3WR

I

WRITE clock input with pull-high resistor

Data on the DATA line are latched into the HT1621 on the rising edge of the

WR signal.

4

DATA

I/O

Serial data input/output with pull-high resistor

5

VSS

¾

Negative power supply, ground

7

OSCI

I

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to

generate a system clock. If the system clock comes from an external clock

source, the external clock source should be connected to the OSCI pad. But

if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads

can be left open.

6

OSCO

O

8

VLCD

I

LCD power input

9

VDD

¾

Positive power supply

10

IRQ

O

Time base or WDT overflow flag, NMOS open drain output

11, 12

BZ, BZ

O

2kHz or 4kHz tone frequency output pair

13~16

COM0~COM3

O

LCD common outputs

48~17

SEG0~SEG31

O

LCD segment outputs

HT1621

Rev. 1.70

4

June 29, 2005