HT9480 datasheet(18/47 Pages) HOLTEK

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HT9480

Rev. 1.20

July 31, 2002

B i t

C O M

9 1 0 1 1 1 2 1 3 1 4 1 5

1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1

S E G M E N T

A d d r e s s

3 2 3 3 3 4

B i t

C O M

S E G M E N T

A d d r e s s

Display memory

Pager decoder

The pager decoder is a POCSAG code pager decoder

at 512, 1200, or 2400 bps data rate, compatible with

CCIR radio paging Code No.1 (POCSAG Code). The

decoder supports six user addresses and six independ-

ently programmable user frames.

The operation of the decoder is controlled by a pager

control address (1EH) in conjunction with a pager data

address (1FH). Upon receipt of a valid call the data

ready interrupt is generated.

· The POCSAG paging code

The CCIR Radio paging Code No.1 (POCSAG Code)

is constructed according to the following rules:

A transmission consists of a preamble followed by a

batch of complete code words. Each batch begins

with a synchronization codeword (SC). The format of

the signal is illustrated in the following Figure.

Each transmission begins with a preamble to achieve

bit synchronization. The preamble is a pattern of one

and zero; 10101010... repeated for a period of at least

576 bits.

Codewords are transmitted in batches. Each batch

consists of a synchronization codeword followed by 8

frames. Each frame consists of 2 codewords. The

eight frames are numbered 0 through 7. All pagers are

similarly divided into 8 groups. Each pager is assigned

to one of the 8 frames according to the 3 least signifi-

cant bits (LSB) of its 21-bit identity code (address).

The 3 bits are called

²Receiver Identity Code² (RIC).

A codeword is either an address or a message code-

word. Idle codewords are transmitted to fill in empty

batches or to separate messages.

An address codeword is coded as shown above. Of

the 21 bits of user addresses, 18 bits are coded in the

codeword itself (bits 2 to 19), which is protected

against transmission errors by a number of CRC

checkbits (bits 22 to 31). Bit 32 is an overall

even-parity bit.

C O M 0

C O M 1

C O M 2

C O M 3

S E G 0

S E G 1

V L C D

2 / 3 V L C D

1 / 3 V L C D

G N D

V L C D

2 / 3 V L C D

1 / 3 V L C D

G N D

V L C D

2 / 3 V L C D

1 / 3 V L C D

G N D

V L C D

2 / 3 V L C D

1 / 3 V L C D

G N D

V L C D

2 / 3 V L C D

1 / 3 V L C D

G N D

V L C D

2 / 3 V L C D

1 / 3 V L C D

G N D

LCD timing

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