MSC8122 datasheet(49/88 Pages) FREESCALE

부품명	MSC8122

상세설명	Quad Core 16-Bit Digital Signal Processor

PDF	88 Pages

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제조업체	FREESCALE [Freescale Semiconductor, Inc]

홈페이지	http://www.freescale.com

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AC Timings

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

2-15

2.5.5.3 DMA Data Transfers

Table 2-16 describes the DMA signal timing.

The DREQ

signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert

DREQ

according to the timings in Table 2-16. Figure 2-7 shows synchronous peripheral interaction.

Table 2-16.

DMA Signals

No.

Characteristic

Ref = CLKIN

Ref = CLKOUT

(1.2 V only)

Units

Min

Max

Min

Max

DREQ set-up time before the 50% level of the falling edge of REFCLK

5.0

—

5.0

—

DREQ hold time after the 50% level of the falling edge of REFCLK

0.5

—

0.5

—

DONE set-up time before the 50% level of the rising edge of REFCLK

5.0

—

5.0

—

DONE hold time after the 50% level of the rising edge of REFCLK

0.5

—

0.5

—

DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge

0.5

7.5

0.5

8.4

Figure 2-7.

DMA Signals

REFCLK

DREQ

DONE

DACK/DONE/DRACK

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