AK4635 datasheet(12/81 Pages) AKM

12 / 81 page

[AK4635]

Rev. 0.6

2007/10

- 12 -

SWITING CHARACTERISTICS

(Ta =

−30 ~ 85°C; AVDD = 2.8 ∼ 3.6V, DVDD = 1.6 ∼ 3.6V, SVDD = 2.2 ∼ 4.0V; CL = 20pF)

Parameter

Symbol

min

typ

max

Units

PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 6)

MCKI Input: Frequency

Pulse Width Low

Pulse Width High

fCLK

tCLKL

tCLKH

11.2896

0.4/fCLK

27.0

MHz

MCKO Output:

Frequency

Duty Cycle except fs=29.4kHz, 32kHz

fs =29.4kHz, 32kHz (Note 28)

fMCK

dMCK

256 x fFCK

kHz

FCK Output: Frequency

Pulse width High

(DIF1-0 bits = “00” and FCKO bit = “1”)

Duty Cycle

(DIF1-0 bits = “00” or FCKO bit = “0”)

fFCK

tFCKH

dFCK

tBCK

kHz

BICK: Period (BCKO1-0 = “00”)

(BCKO1-0 = “01”)

(BCKO1-0 = “10”)

Duty Cycle

tBCK

dBCK

1/16fFCK

1/32fFCK

1/64fFCK

Audio Interface Timing

DSP Mode: (Figure 7, Figure 8)

FCK “

↑” to BICK “↑” (Note 29)

FCK “

↑” to BICK “↓” (Note 30)

BICK “

↑” to SDTO (BCKP = “0”)

BICK “

↓” to SDTO (BCKP = “1”)

SDTI Hold Time

SDTI Setup Time

tDBF

tBSD

tSDH

tSDS

0.5 x tBCK

−40

0.5 x tBCK

−40

-70

0.5 x tBCK

0.5 x tBCK + 40

0.5 x tBCK +40

Except DSP Mode: (Figure 9)

BICK “

↓” to FCK Edge

FCK to SDTO (MSB)

(Except I2S mode)

BICK “

↓” to SDTO

SDTI Hold Time

SDTI Setup Time

tBFCK

tFSD

tBSD

tSDH

tSDS

−40

−70

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