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GL800HT25 데이터시트(PDF) 18 Page - GENESYS LOGIC

부품명 GL800HT25
상세설명  USB 2.0 UTMI Compliant Transceiver IP Core
PDF  20 Pages
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제조업체  GENESYS [GENESYS LOGIC]
홈페이지  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL800HT25 데이터시트(HTML) 18 Page - GENESYS LOGIC

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GL800HT25 USB 2.0 UTMI Compliant Transceiver IP Core
©2000-2003 Genesys Logic Inc.—All rights reserved.
Page 18
5.3 Timing Chart
5.3.1 CLK30 Rising and Falling Edge VS. Input/Output Signals
* Output signals includes TXRDY, RXACTV, RXERR, RXVLD, LINEST[1:0], D[15:0]
** Input signals includes TXVLD, VALIDH
Figure 5.5 - CLK30 Rising and Falling Edge VS. Input/Output Signals
Max.
Min.
Unit
T1
8
-
ns
T2
3
-
ns
T3
-
8
ns
T1
T2
T3
CLK30
OUTPUT (*)
INPUT (**)



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