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GL842 데이터시트(PDF) 49 Page - GENESYS LOGIC

부품명 GL842
상세설명  USB 2.0 2-in-1 Scanner Controller
PDF  64 Pages
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제조업체  GENESYS [GENESYS LOGIC]
홈페이지  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL842 데이터시트(HTML) 49 Page - GENESYS LOGIC

Back Button GL842 Datasheet HTML 45Page - GENESYS LOGIC GL842 Datasheet HTML 46Page - GENESYS LOGIC GL842 Datasheet HTML 47Page - GENESYS LOGIC GL842 Datasheet HTML 48Page - GENESYS LOGIC GL842 Datasheet HTML 49Page - GENESYS LOGIC GL842 Datasheet HTML 50Page - GENESYS LOGIC GL842 Datasheet HTML 51Page - GENESYS LOGIC GL842 Datasheet HTML 52Page - GENESYS LOGIC GL842 Datasheet HTML 53Page - GENESYS LOGIC Next Button
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GL842 USB 2.0 2-in-1 Scanner Controller
Genesys Logic Inc.—All rights reserved.
Page 49
Offset 7Ah ……..……..……………..………..…...………..….………..…..…. Default value = 8’h00
X
X
X
X
X
X
CK4MAP17 CK4MAP16
X
X
X
X
X
X
R/W
R/W
7-2 RESERVED
-
1-0 CK4MAP[17:16] CCD clock 4 bits mapping function.
Offset 7Bh ……..……..………………..……..…..….………..….………..…..…. Default value = 8’h00
CK4MAP15 CK4MAP14 CK4MAP13 CK4MAP12 CK4MAP11 CK4MAP10 CK4MAP9 CK4MAP8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 CK4MAP[15:8] CCD clock 4 bits mapping function.
Offset 7Ch ……..……..……………..………....….………..….………..…..…. Default value = 8’h00
CK4MAP7 CK4MAP6 CK4MAP5 CK4MAP4 CK4MAP3 CK4MAP2 CK4MAP1 CK4MAP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 CK4MAP[7:0] CCD clock 4 bits mapping function.
Offset 7Dh ……..……..………………..………..…………..….………..…..…. Default value = 8’h00
CK1NEG
CK3NEG
CK4NEG
RSNEG
CPNEG
BSMPNEG VSMPNEG DLYSET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7 CK1NEG
0 CCD clock1,clock2 output locate at positive edge position of system clock.
1 CCD clock1,clock2 output locate at negative edge position of system clock.
6 CK3NEG
0 CCD clock3 output locate at positive edge position of system clock.
1 CCD clock3 output locate at negative edge position of system clock.
5 CK4NEG
0 CCD clock4 output locate at positive edge position of system clock.
1 CCD clock4 output locate at negative edge position of system clock.
4 RSNEG
0 CCD RS output locate at positive edge position of system clock.
1 CCD RS output locate at negative edge position of system clock.
3 CPNEG
0 CCD CP output locate at positive edge position of system clock.
1 CCD CP output locate at negative edge position of system clock.
2 BSMPNEG
0 AFE video sample output locate at positive edge position of system clock.
1 AFE video sample output locate at negative edge position of system clock.
1 VSMPNEG
0 AFE dark sample output locate at positive edge position of system clock.
1 AFE dark sample output locate at negative edge position of system clock.
0 DLYSET
0 Disable this function.
1 To enable VSMP and BSMP to delay output by 8.33ns unit



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