GL852 USB 2.0 MTT HUB Controller

©2000-2007 Genesys Logic Inc. - All rights reserved.

Page 14

Clock and Reset Interface

GL852

GL852

Pin Name

64Pin#

48Pin#

I/O Type

Description

X1

20

14

I

12MHz crystal clock input.

X2

21

15

O

12MHz crystal clock output.

RESET#

38

26

I

Active low. External reset input, default pull high 10K .

When RESET# = low, whole chip is reset to the initial

state.

System Interface

GL852

GL852

Pin Name

64 Pin#

48Pin#

I/O Type

Description

TEST

39

27

I

(pd)

0: Normal operation.

1: Chip will be put in test mode.

Power / Ground

GL852

GL852

Pin Name

64 Pin#

48Pin#

I/O Type

Description

AVDD

11,18,22,

28,64

1,7,12,16,19

P

3.3V analog power input for analog circuits.

AGND

1,12,19,

23,29

2,8,13,20,

P

Analog ground input for analog circuits.

DVDD

37,47,

52,59

25,34,38,44,

48

P

3.3V digital power input for digital circuits

DGND

36,46,

51,58,62

47

P

Digital ground input for digital circuits.

NC

2,5~7,10,

13,16,24,

27,30,33

-

-

No connection

Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power

routing and the ground plane. For detailed information, please refer to GL852 Design Guideline.

Notation:

Type

O

Output

I

Input

B

Bi-directional

B/I

Bi-directional, default input

B/O

Bi-directional, default output

P

Power / Ground

A

Analog

SO

Automatic output low when suspend

pu

Internal pull up

pd

Internal pull down

odpu

Open drain with internal pull up