R2010

R

R

FAST ETHERNET RISC PROCESSOR

Specifications subject to change without notice, contact your sales representatives for the most update information.

Page 2 of 4

REV 1.0 Nov. 28 2005

1.

Features

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Five-stage pipeline

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RISC architecture

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Bus interface

- Multiplexed address and Data bus

- Supports non-multiplexed address bus A [20:0]

- 16-bit external bus dynamic access

- 16M-byte memory address space

- 64K-byte I/O space

- Supports an independent data/address bus for

external I/O device

- Supports a glueless and simplified 16-bit

PCMCIA bus interface

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Supports two compatible UART serial channels

with 16-byte FIFO and hardware flow-control.

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Supports CPU ID

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SDRAM control Interface

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Three independent 16-bit timers and one independent

programmable watchdog timer

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The Interrupt controller with five maskable

external interrupts

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Two independent DMA channels

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Programmable chip-select logic for Memory

or I/O bus cycle decoder

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Programmable wait-state generator

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With 8-bit or 16-bit Boot ROM bus size

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1-Port Fast Ethernet MAC with MII interface

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Supports an 8K-byte Uniform cache

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With 25MHz input frequency and up to 100MHz

maximum internal frequency.

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Compatible with 3.3V I/O and 2.5V core voltage.

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Package Type includes 128-pin PQFP.