MPC8280 datasheet(239/1386 Pages) FREESCALE

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MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

III-1

Part III

The Hardware Interface

Intended Audience

Part III is intended for system designers who need to understand how each MPC8280 signal works and

how those signals interact.

Contents

Part III describes external signals, clocking, memory control, and power management of the MPC8280.

It contains the following chapters:

•

Chapter 6, “External Signals,” shows a functional pinout of the MPC8280 and describes the

MPC8280 signals.

•

Chapter 7, “60x Signals,” describes signals on the 60x bus.

•

Chapter 8, “The 60x Bus,” describes the operation of the bus used by PowerPC processors.

•

Chapter 10, “Clocks and Power Control,” describes the clocking architecture of the MPC8280.

•

Chapter 9, “PCI Bridge,” describes how the PCI bridge enables the MPC8280 to bridge PCI agents

gluelessly to a host processor that implements the PowerPC architecture and how it is compliant

with PCI Specification Revision 2.2.

•

Chapter 11, “Memory Controller,” describes the memory controller, which controlling a maximum

of eight memory banks shared between a general-purpose chip-select machine (GPCM) and three

user-programmable machines (UPMs).

•

Chapter 12, “Secondary (L2) Cache Support,” provides information about implementation and

configuration of a level-2 cache.

•

Chapter 13, “IEEE 1149.1 Test Access Port,” describes the dedicated user-accessible test access

port (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and

Boundary Scan Architecture.

MPC8280 데이터시트(PDF) 239 Page - Freescale Semiconductor, Inc