MPC8280 datasheet(282/1386 Pages) FREESCALE

282 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

8-6

Freescale Semiconductor

The MPC8280 controls bus access through the bus request (BR) and bus grant (BG) signals. It determines

the state of the address and data bus busy signals by monitoring DBG, TS, AACK, and TA, and it qualifies

them with ABB and DBB.

The following signals are used for address bus arbitration:

•BR (bus request)—A device asserts BR to request address bus mastership.

•BG (bus grant)—Assertion indicates that a bus device may, with proper qualification, assume

mastership of the address bus. A qualified bus grant occurs when BG is asserted while ABB and

ARTRY are negated.

•ABB (address bus busy)—A device asserts ABB to indicate it is the current address bus master.

Note that if all devices assert ABB with TS and would normally negate ABB after AACK is

asserted, the devices can ignore ABB because the MPC8280 can internally generate ABB. The

MPC8280’s ABB, if enabled, must be tied to a pull-up resistor.

The following signals are used for data bus arbitration:

•DBG (data bus grant)—Indicates that a bus device can, with the proper qualification, assume data

bus mastership. A qualified data bus grant occurs when DBG is asserted while DBB and ARTRY

are negated.

•DBB (data bus busy)—Assertion by the device indicates that the device is the current data bus

master. The device master always assumes data bus mastership if it needs the data bus and is given

a qualified data bus grant (see DBG). Note that if all devices assert DBB in conjunction with

qualified data bus grant and would normally negate DBB after the last TA is asserted, the devices

can ignore DBB because the MPC8280 can generate DBB internally. The MPC8280’s DBB signal,

if enabled, must be tied to a pull-up resistor.

The following is a summary of rules for arbitration:

•

Preference among devices is determined at the request level. The MPC8280 supports eight levels

of bus requests.

•

When no bus device is requesting the address bus, the MPC8280 parks the device selected in the

arbiter configuration register on the bus.

For more information, see Section 4.3.2.2, “60x Bus Arbiter Configuration Register (PPC_ACR).”

8.3.2

Address Pipelining and Split-Bus Transactions

The 60x bus protocol provides independent address and data bus capability to support pipelined and

split-bus transaction system organizations. Address pipelining allows the next address tenure to begin

before the current data tenure has finished. Although this ability does not inherently reduce memory

latency, support for address pipelining and split-bus transactions can greatly improve effective

bus/memory throughput. These benefits are most fully realized in shared-memory, multiple-master

implementations where bus bandwidth is critical to system performance.

External arbitration (as provided by the MPC8280) is required in systems in which multiple devices share

the system bus. The MPC8280 uses the address acknowledge (AACK) signal to control pipelining. The

MPC8280 supports both one- and zero-level bus pipelining. One-level pipelining is achieved by asserting

AACK to the current address bus master and granting mastership of the address bus to the next requesting

MPC8280 데이터시트(PDF) 282 Page - Freescale Semiconductor, Inc

MPC8280 데이터시트(HTML) 282 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL