MPC8280 datasheet(297/1386 Pages) FREESCALE

297 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-21

Extended transfer mode is enabled by setting the BCR[ETM].

8.4.4

Address Transfer Termination

Address transfer termination occurs with the assertion of the address acknowledge (AACK) signal, or

retried with the assertion of ARTRY. ARTRY must remain asserted until one clock after AACK; the bus

clock cycle after AACK is called the ARTRY window. The MPC8280 controls assertion of AACK unless

the cycle is claimed by an external slave, such as an external L2 cache controller. Following the assertion

of L2_HIT, the L2 cache controller is responsible for asserting AACK. When AACK is asserted by the

external slave, it should be asserted for one clock cycle and then negated for one clock cycle before

entering a high-impedance state. The MPC8280 holds AACK in a high-impedance state until it is required

to assert AACK to terminate the address cycle.

The MPC8280 uses AACK to enforce a pipeline depth of one to its internal slaves.

8.4.4.1

Address Retried with ARTRY

The address transfer can be terminated with the requirement to retry if ARTRY is asserted during the

address tenure and through the cycle following AACK. The assertion causes the entire transaction (address

and data tenure) to be rerun. As a snooping device, the MPC8280 processor asserts ARTRY for a snooped

transaction that hits modified data in the data cache that must be written back to memory, or if the snooped

transaction could not be serviced. As a bus master, the MPC8280 responds to an assertion of ARTRY by

aborting the bus transaction and requesting the bus again, as shown in Figure 8-7. Note that after

recognizing an assertion of ARTRY and aborting the current transaction, the MPC8280 may not run the

same transaction the next time it is granted the bus.

7-Byte

Byte

6-Byte

Half

5-Byte

6-Byte

Word

3-Byte

4-Byte

xxxx

Double

Stop

Table 8-12. Address and Size State for Extended Transfers (continued)

Size State [0–3]

Address State[0–4]

Port Size

Next Size State [0–3]

Next Address State[0–4]

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