MPC8280 datasheet(306/1386 Pages) FREESCALE

306 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

8-30

Freescale Semiconductor

When the MPC8280 processor is not the address bus master, GBL is an input. The MPC8280 processor

snoops a transaction if TS and GBL are asserted together in the same bus clock cycle (a qualified snooping

condition). No snoop update to the MPC8280 processor cache occurs if the transaction is not marked

global. This includes invalidation cycles.

When the MPC8280 processor detects a qualified snoop condition, the address associated with the TS is

compared against the data cache tags. Snooping completes if no hit is detected. However, if the address

hits in the cache, the MPC8280 processor reacts according to the MEI protocol shown in Figure 8-12. This

figure assumes that WIM = 0b001 (memory space is marked for write-back, caching-allowed, and

coherency-enforced modes).

Figure 8-12. MEI Cache Coherency Protocol—State Diagram (WIM = 001)

8.7

Processor State Signals

This section describes the MPC8280’s support for atomic update and memory through the use of the

lwarx/stwcx. instruction pair. It also describes the TLBISYNC input.

Invalid

Modified

SH/CRW

SH = Snoop hit

RH = Read hit

WH = Write hit

WM = Write miss

RM = Read miss

SH/CRW = Snoop hit, cacheable read/write

SH/CIR = Snoop hit, cache-inhibited read

= Snoop push

= Cache line fill

Exclusive

SH/CRW

SH/CIR

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