MPC8280 datasheet(412/1386 Pages) FREESCALE

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Clocks and Power Control

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

10-2

Freescale Semiconductor

10.1.2

Core PLL

The core PLL has the same advantages as the main PLL; it performs frequency multiplication and skew

elimination for the core blocks. The core PLL input clock is synchronous with the 60x bus clock. Its

configuration word, CORE_PLL_CFG[0-4], is determined by the MPC8280 clock configuration mode

setting. According to the setting, the core PLL multiplies the internal bus clock and synchronously

provides the core clocks.

10.1.3

Skew Elimination

The PLL can tighten synchronous timings by eliminating skew between phases of the internal clock and

the external clock entering the chip (CLKIN). Skew elimination is always active when the PLL is enabled.

Disabling the PLL (PLL bypass) can greatly increase clock skew.

10.1.4

Dividers

The PLL output clock, MAIN_CLK, is twice the CPM clock. MAIN_CLK applies to general-purpose

dividers. Each MPC8280 internal clock is generated by a dedicated divisor which is a programmable

number between 1 and 16. Dividers are determined by the clock configuration modes that are selected by

seven bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits

from hardware configuration word[28–31] (MODCK_H). For complete lists of these dividers, refer to the

MPC8280 PowerQUICC II Family Hardware Specifications (order number: MPC8280EC). Note that all

dividers’ output clocks have identical skew in relation to the input clock because the delay through the

dividers for all clocks is identical independent of how its dividers have been programmed.

10.1.5

Internal Clock Signals

The internal logic of the MPC8280 generates the next internal clock lines:

•

CPM general system clocks (CPM_CLK)

•

60x bus and local bus (BUS_CLK). Identical to CLKIN.

•

SCC clocks (SCC_CLK)

•

Baud-rate generator clock (BRG_CLK)

•

PCI clock (PCI_CLK)

•

DLL clocks

The PLL synchronizes these clock signals to each other.

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