MPC8280 datasheet(595/1386 Pages) FREESCALE

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Serial Interface with Time-Slot Assigner

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

15-17

15.5

Serial Interface Registers

The serial interface registers are described in the following sections. The MCC configuration registers,

which define the TDM mapping of the MCC channels, are described in Section 29.6, “MCC Configuration

Registers (MCCFx).”

NOTE

The programming of SI registers and SIx RAM must be coherent with the

MCCF programming.

15.5.1

SI Global Mode Registers (SI

xGMR)

The SI global mode registers (SIxGMR), shown in Figure 15-10, defines the activation state of the TDM

channels for each SI.

Figure 15-4 describes SIxGMR.

15.5.2

SI Mode Registers (SI

xMR)

There are eight SI mode registers (SIxMR), shown in Figure 15-11, one for each TDM channel (SIxAMR,

SIxBMR, SIxCMR, and SIxDMR). They are used to define SI operation modes and allow the user (with

SIx RAM) to support any or all of the ISDN channels independently when in IDL or GCI mode. Any extra

serial channel can then be used for other purposes.

01234567

Field

STZD

STZC

STZB

STZA

END

ENC

ENB

ENA

Reset

0000_0000

R/W

Addr

11B28 (SI1GMR), 11B48 (SI2GMR)

Figure 15-10. SI Global Mode Registers (SI

xGMR)

Table 15-4. SI

xGMR Field Descriptions

Bit

Name

Description

0–3

STZx

Program L1TXDx to zero for TDM a, b, c or d

0 Normal operation

1 L1TXDx = 0 until serial clocks are available, which is useful for GCI activation. See

Section 15.7.1, “SI GCI Activation/Deactivation Procedure.”

4–7

ENx

Enable TDMx. Note that enabling a TDM is the last step in initialization.

0 TDM channel x is disabled. The SI

x RAMs and routing for TDMx are in a state of reset, but all

other SI functions still operate.

1 All TDMx functions are enabled.

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