MPC8280 datasheet(629/1386 Pages) FREESCALE

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CPM Multiplexing

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

16-17

2–4

RS1CS Receive SCC1 clock source (NMSI mode). Ignored if SCC1 is connected to the TSA (SC1 = 1).

000 SCC1 receive clock is BRG1.

001 SCC1 receive clock is BRG2.

010 SCC1 receive clock is BRG3.

011 SCC1 receive clock is BRG4.

100 SCC1 receive clock is CLK11.

101 SCC1 receive clock is CLK12.

110 SCC1 receive clock is CLK3.

111 SCC1 receive clock is CLK4.

5–7

TS1CS

Transmit SCC1 clock source (NMSI mode). Ignored if SCC1 is connected to the TSA (SC1 = 1).

000 SCC1 transmit clock is BRG1.

001 SCC1 transmit clock is BRG2.

010 SCC1 transmit clock is BRG3.

011 SCC1 transmit clock is BRG4.

100 SCC1 transmit clock is CLK11.

101 SCC1 transmit clock is CLK12.

110 SCC1 transmit clock is CLK3.

111 SCC1 transmit clock is CLK4.

GR2

Grant support of SCC2

0 SCC2 transmitter does not support the grant mechanism. The grant is always asserted internally.

1 SCC2 transmitter supports the grant mechanism as determined by the GMx bit of a serial device

channel.

SC2

SCC2 connection

0 SCC2 is not connected to the TSA and is either connected directly to the NMSIx pins or is not

used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O

control register.

1 SCC2 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.

10–12

RS2CS Receive SCC2 clock source (NMSI mode). Ignored if SCC2 is connected to the TSA (SC2 = 1).

000 SCC2 receive clock is BRG1.

001 SCC2 receive clock is BRG2.

010 SCC2 receive clock is BRG3.

011 SCC2 receive clock is BRG4.

100 SCC2 receive clock is CLK11.

101 SCC2 receive clock is CLK12.

110 SCC2 receive clock is CLK3.

111 SCC2 receive clock is CLK4.

13–15

TS2CS

Transmit SCC2 clock source (NMSI mode). Ignored if SCC2 is connected to the TSA (SC2 = 1).

000 SCC2 transmit clock is BRG1.

001 SCC2 transmit clock is BRG2.

010 SCC2 transmit clock is BRG3.

011 SCC2 transmit clock is BRG4.

100 SCC2 transmit clock is CLK11.

101 SCC2 transmit clock is CLK12.

110 SCC2 transmit clock is CLK3.

111 SCC2 transmit clock is CLK4.

GR3

Grant support of SCC3

0 SCC3 transmitter does not support the grant mechanism. The grant is always asserted internally.

1 SCC3 transmitter supports the grant mechanism as determined by the GMx bit of a serial device

channel.

Table 16-6. CMXSCR Field Descriptions (continued)

Bits

Name

Description

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