MPC8280 datasheet(726/1386 Pages) FREESCALE

726 / 1386 page

SCC UART Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

21-20

Freescale Semiconductor

Figure 21-10. SCC UART Interrupt Event Example

SCCE bits are cleared by writing ones; writing zeros has no effect. Unmasked bits must be cleared before

the CPM clears an internal interrupt request. Figure 21-11 shows SCCE/SCCM for UART operation.

Field

—

IDL

GRA BRKE BRKS

—

CCR BSY

Reset

0000_0000_0000_0000

R/W

Addr

0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)

0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)

Figure 21-11. SCC UART Event Register (SCCE) and Mask Register (SCCM)

IDL

CCR

IDL

IDL BRKS

BRKE IDL CD

Break

Line Idle

10 Characters

RXD

Characters

Received by UART

Time

Line Idle

TXD

RTS

Characters

Transmitted by UART

CTS

Line Idle

7 Characters

Notes:

UART SCCE

Events

1. The first RX event assumes Rx buffers are 6 bytes each.

2. The second IDL event occurs after an all-ones character is received.

3. The second RX event position is programmable based on the MAX_IDL value.

4. The BRKS event occurs after the first break character is received.

5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.

Legend:

A receive control character defined not to be stored in the Rx buffer.

Notes:

UART SCCE

Events

1. TX event assumes all seven characters were put into a single buffer and TxBD[CR]=1.

2. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.

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