MPC8280 datasheet(790/1386 Pages) FREESCALE

790 / 1386 page

SCC Ethernet Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

25-2

Freescale Semiconductor

Figure 25-2. Ethernet Block Diagram

The MPC8280 Ethernet controller requires an external serial interface adaptor (SIA) and transceiver

function to complete the interface to the media.

Although the MPC8280 contains DPLLs that allow Manchester encoding and decoding, these DPLLs

were not designed for Ethernet rates. Therefore, the MPC8280 Ethernet controller bypasses the on-chip

DPLLs and uses the external system interface adaptor on the EEST instead. The on-chip DPLL cannot be

used for low-speed (1-Mbps) Ethernet either because it cannot properly detect start-of-frame or

end-of-frame.

Note that the CPM of the MPC8280 requires a minimum system clock frequency of 24 MHz to support

Ethernet.

25.2

Features

The following list summarizes the main features of the SCC in Ethernet mode:

•

Performs MAC layer functions of Ethernet and IEEE 802.3

•

Performs framing functions

— Preamble generation and stripping

— Destination address checking

— CRC generation and checking

— Automatically pads short frames on transmit

— Framing error (dribbling bits) handling

•

Full collision support

— Enforces the collision (jamming)

— Truncated binary exponential backoff algorithm for random wait

Shifter

Receiver

Control

Unit

FIFO

Shifter

Transmitter

Control

Unit

FIFO

Slot Time

Clock

Generator

Internal Clocks

Control

Registers

TXD

RXD

Peripheral Bus

Data

RCLK

TCLK

and Defer

Counter

RTS = TENA

CD = RENA

CTS = CLSN

CD = RENA

REJECT

RSTRT

60x Bus

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