MPC8280 datasheet(868/1386 Pages) FREESCALE

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Serial Management Controllers (SMCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

28-14

Freescale Semiconductor

28.3.9

SMC UART RxBD

Using the BDs, the CP reports information about the received data on a per-buffer basis. Then it closes the

current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the

following occurs:

•

An error is received during message processing

•

A full receive buffer is detected

•

A programmable number of consecutive idle characters are received

Figure 28-6 shows the format of the SMC UART RxBD.

Table 28-7 describes RxBD fields.

0123

456

789

Offset + 0

—

Offset + 2

Data Length

Offset + 4

Rx Data Buffer Pointer

Offset + 6

Figure 28-6. SMC UART RxBD

Table 28-7. SMC UART RxBD Field Descriptions

Bit

Name

Description

Empty.

0 The buffer is full or data reception stopped due to an error. The core can read or write any fields

of this RxBD. The CP does not use this BD while E is zero.

1 The buffer is empty or reception is in progress. This RxBD and its buffer are owned by the CP.

Once E is set, the core should not write any fields of this RxBD.

—

Reserved, should be cleared.

Wrap (last BD in RxBD table).

0 Not the last BD in the table.

1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that

RBASE points to in the table. The number of RxBDs in this table is determined only by the W bit

and overall space constraints of the dual-port RAM.

Interrupt.

0 No interrupt is generated after this buffer is filled.

1 The SMCE[RXB] is set when this buffer is completely filled by the CP, indicating the need for the

core to process the buffer. RXB can cause an interrupt if it is enabled.

4–5

—

Reserved, should be cleared.

Continuous mode.

0 Normal operation.

1 The CP does not clear the E bit after this BD is closed, allowing the CP to automatically overwrite

the buffer when it next accesses the BD. However, E is cleared if an error occurs during reception,

regardless of how CM is set.

Buffer closed on reception of idles. Set when the buffer has closed because a programmable

number of consecutive idle sequences is received. The CP writes ID after received data is in the

buffer.

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