MPC8280 datasheet(880/1386 Pages) FREESCALE

880 / 1386 page

Serial Management Controllers (SMCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

28-26

Freescale Semiconductor

28.4.8

SMC Transparent RxBD

Using BDs, the CP reports information about the received data for each buffer and closes the current

buffer, generates a maskable interrupt, and starts to receive data into the next buffer after one of the

following events:

•

An overrun error occurs.

•

A full receive buffer is detected.

•

The ENTER HUNT MODE command is issued.

Table 28-13 describes SMC transparent RxBD fields.

123

456

789

Offset + 0

—

—OV

—

Offset + 2

Data Length

Offset + 4

Rx Data Buffer Pointer

Offset + 6

Figure 28-13. SMC Transparent RxBD

Table 28-13. SMC Transparent RxBD Field Descriptions

Bits

Name

Description

Empty.

0 The buffer is full or reception was aborted due to an error. The core can read or write any fields

of this RxBD. The CP does not use this BD while E = 0.

1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the

core should not write any fields of this RxBD.

—

Reserved, should be cleared.

Wrap (last BD in RxBD table).

0 Not the last BD in the table.

1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that

RBASE points to. The number of RxBDs is determined only by the W bit and overall space

constraints of the dual-port RAM.

Interrupt.

0 No interrupt is generated after this buffer is filled.

1 SMCE[RXB] is set when the CP completely fills this buffer indicating that the core must process

the buffer. The RXB bit can cause an interrupt if it is enabled.

4–5

—

Reserved, should be cleared.

Continuous mode.

0 Normal operation.

1 The CP does not clear E after this BD is closed, allowing the buffer to be overwritten when the

CP next accesses this BD. However, E is cleared if an error occurs during reception, regardless

of how CM is set.

7–13

—

Reserved, should be cleared.

Overrun. Set when a receiver overrun occurs during reception. The CP writes OV after the received

data is placed into the buffer.

—

Reserved, should be cleared.

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