MPC8280 datasheet(994/1386 Pages) FREESCALE

994 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-34

Freescale Semiconductor

Figure 31-21. ATM-to-TDM Interworking

When going from TDM to ATM, the MCC receiver routes data from the TDM line to a specific BD table.

The ATM controller transmitter is programmed to operate on the same table. When the MCC fills a receive

buffer, the ATM controller sends it. The two controllers synchronize on the MCC’s RxBD[E] and the ATM

controller’s TxBD[R].

When going from ATM to TDM, the ATM receiver reassembles data received from a particular channel to

a specific BD table. The MCC transmitter is programmed to operate on the same table. When the ATM

controller fills a receive buffer, the MCC controller sends it. The controllers synchronize on the ATM

controller’s RxBD[E] and the MCC’s TxBD[R].

The MCC and ATM receivers must be programmed to operate in opposite E-bit polarity. That is, both

receivers receive data into buffers whose RxBD[E] = 0 and set RxBD[E] when a buffer is full. For the ATM

receiver, set RCT[INVE] of the AAL1- and AAL0-specific areas of the receive connection table; see

Section 31.10.2.2, “Receive Connection Table (RCT).” For the MCC receiver, set CHAMR[EP]; see

Section 29.3.2.3, “Channel Mode Register (CHAMR)—Transparent Mode.”

31.9.2

Using Interrupts in Automatic Data Forwarding

The core can program the MCC and ATM interrupt mechanism to trigger interrupts for events such as a

buffer closing or transfer errors. The interrupt mechanism can be used to synchronize the start of the

automatic bridging process. For example, to start the MCC transmitter after a specific buffer reaches the

ATM receiver (the buffering is required to cope with the ATM network’s CDV), set ATM RxBD[I]. When

the receive buffer is full, the RxBD is closed, RxBD[E] is set (because it is operating in opposite E-bit

polarity), and the core is interrupted. The core then starts the MCC transmitter.

MCC

Transmitter

TDM Interface

Buffer 1

Buffer 2

Buffer 3

Buffer 4

Buffer 5

ATM*

Receiver

UTOPIA Interface

BD Table

0BD 1

1BD 2

1BD 3

0BD 4

0BD 5

MCC Tx ptr

ATM Rx ptr

ATM

Transmitter

UTOPIA Interface

Buffer 1

Buffer 2

Buffer 3

Buffer 4

Buffer 5

MCC*

Receiver

TDM Interface

BD Table

0BD 1

1BD 2

1BD 3

0BD 4

0BD 5

ATM Tx ptr

MCC Rx ptr

* The MCC and ATM receivers should be programmed to operate in opposite polarity E (empty) bit.

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