MPC8280 datasheet(1025/1386 Pages) FREESCALE

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ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

31-65

Figure 31-41. Transmit Buffers and BD Table Example

31.10.5.2 Receive Buffer Operation

For AAL5 channels, the user should choose to operate in static buffer allocation or in global buffer

allocation by writing to RCT[BUFM]. AAL1 CES and AAL0 channels must use static buffer allocation.

31.10.5.2.1

Static Buffer Allocation

The user prepares a table of BDs pointing to the receive buffers. The address of the first BD is put in the

channel’s RCT[RBD_BASE]. When an ATM cell arrives, the CP opens the first BD in the table and starts

filling its associated buffer with received data. When the current buffer is full, the CP increments

RBD_Offset, which is the offset to the current BD from RBD_BASE, and reads the next BD in the table.

If the BD is empty (RxBD[E] = 1), the CP continues receiving. If the BD is not empty, a busy condition

has occurred and a busy interrupt is sent to the event queue.

Figure 31-42 shows the empty bit in the RxBD tables and their associated buffers for two example ATM

channels.

Tx Buffer 1 of Channel 1

Tx Buffer 2 of Channel 1

Tx Buffer 3 of Channel 1

Tx Buffer 4 of Channel 1

Tx Buffer 5 of Channel 1

Ch1 TxBD Table

0BD 1

1BD 2

1BD 3

0BD 4

0BD 5

TBD_BASE

TBD_Offset

Note: The shaded buffers are ready to be sent; unshaded buffers are waiting to be prepared.

Ch1 TxBD Table

Pointers in the TCT

Tx Buffer 1 of Channel 4

Tx Buffer 2 of Channel 4

Tx Buffer 3 of Channel 4

Tx Buffer 4 of Channel 4

Tx Buffer 5 of Channel 4

Ch4 TxBD Table

1BD 1

0BD 2

0BD 3

0BD 4

0BD 5

TBD_BASE

TBD_Offset

Ch4 TxBD Table

Pointers in the TCT

1BD 6

BD 7

Tx Buffer 6 of Channel 4

Tx Buffer 7 of Channel 4

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